机続き。まずはプレソルベントで掃除。エアブローしても結構な粉塵が表面に
残ってる。ロックエースのマルチトップクリアーQ 10:1型を主剤150g、トータ
ル180g程度で、ガン吹き。枠組み部分なんかはほとんどミストになってしまう
ので効率悪い。2回ほど吹いて使い切り。これは目止めくらい。
H8SX続き。SCI4で通信します。H8SXは最近のチップだけあって省電力設計がしっ かりしてる。日立のシリアルといえばSCI。このSCIはH8/3052に近い。同じじゃ ないけど。SCIと名前がついていてもそれはハードの基本構造だけ同じというだ けなので毎回きっちり調べないといけない。周辺デバイスは融通無碍なんだよね。
putc/getcまでできれば、後はお気楽だ(LEDに較べれば)。
H8SX続き。SCI4で通信します。H8SXは最近のチップだけあって省電力設計がしっ かりしてる。日立のシリアルといえばSCI。このSCIはH8/3052に近い。同じじゃ ないけど。SCIと名前がついていてもそれはハードの基本構造だけ同じというだ けなので毎回きっちり調べないといけない。周辺デバイスは融通無碍なんだよね。
putc/getcまでできれば、後はお気楽だ(LEDに較べれば)。
#include <types.h>
#define PM3_DDR ((volatile uint8_t *)0xffee50)
#define PM3_DR ((volatile uint8_t *)0xffee51)
// ビット構成はH8/3052と同じ。
#define _SCI4_BASE 0xfffe90
/* Serial Mode Register R/W */
#define _SCI_SMR 0
#define SMR_CM 0x80 /* Communication Mode (1:clock)*/
#define SMR_CHR 0x40 /* Character Length (0:8bit) */
#define SMR_PE 0x20 /* Parity Enable */
#define SMR_PM 0x10 /* Parity Mode (0:even) */
#define SMR_STOP 0x08 /* Stop bit length (0: 1stopbit) */
#define SMR_MP 0x04 /* Multi Processor mode */
#define SMR_CKS1 0x02 /* ClocK Select 1 */
#define SMR_CKS0 0x01 /* ClocK Select 0 */
/* Bit Rate Register */
#define _SCI_BRR 1
/* Serial Control Register R/W */
#define _SCI_SCR 2
#define SCR_TIE 0x80 /* Transmit Interrupt Enable */
#define SCR_RIE 0x40 /* Receive Interrupt Enable */
#define SCR_TE 0x20 /* Transmit Enable */
#define SCR_RE 0x10 /* Receive Enable */
#define SCR_MPIE 0x08 /* Multi Processor Interrupt Enable */
#define SCR_TEIE 0x04 /* Transmit End Interrupt Enable */
#define SCR_CKE1 0x02 /* ClocK Enable 1 */
#define SCR_CKE0 0x01 /* ClocK Enable 0 */
/* Transmit Data Register R/W */
#define _SCI_TDR 3
/* Serial Status Register R/(W) */
#define _SCI_SSR 4
#define SSR_TDRE 0x80 /* Transmit Data Register Empty (0 write only)*/
#define SSR_RDRF 0x40 /* Receive Data Register Full (0 write only)*/
#define SSR_ORER 0x20 /* OverRun ERror (0 write only)*/
#define SSR_FER 0x10 /* Framing ERror (0 write only)*/
#define SSR_PER 0x08 /* Parity ERror (0 write only)*/
#define SSR_TEND 0x04 /* Transmit END (read only)*/
#define SSR_MPB 0x02 /* MultiProcessor Bit (read only)*/
#define SSR_MPBT 0x01 /* MultiProcessor Bit Transfer */
#define SSR_ERR_BITS (SSR_ORER | SSR_FER | SSR_PER)
/* Receive Data Register */
#define _SCI_RDR 5
//これはH8/3052にはなくH8SX/1655の設定。
/* Smart Card Mode Register */
#define _SCI_SCMR 6
#define SCMR_SDIR 0x08
#define SCMR_SINV 0x04
#define SCMR_SMIF 0x01 /* SMart card InterFace Select */
#define SCI(n, r) ((volatile uint8_t *)_SCI ## n ## _BASE + _SCI_ ## r)
// このレジスタを設定しないと周辺モジュールのポートが入力設定にならない
/* Input buffer Control Register 1:Enable, 0:Disable */
#define P6_ICR ((volatile uint8_t *)0xfffb95)
// 省電力用のモジュールの有効化の設定。
/* Module SToP Control Register B */
#define MSTPCRB ((volatile uint16_t *)0xfffdca)
void sci4_init (void);
int8_t sci4_getc (void);
void sci4_putc (int8_t);
void
machine_startup ()
{
int8_t c;
*PM3_DDR |= 8;
*PM3_DR &= ~8; // LED on.
sci4_init ();
sci4_putc ('o');
sci4_putc ('h');
sci4_putc ('a');
sci4_putc ('y');
sci4_putc ('o');
sci4_putc ('\r');
sci4_putc ('\n');
while ((c = sci4_getc ()))
sci4_putc (c);
// Error. SCI4の受信でエラーがあればここに来ます。
*PM3_DR |= 8; // LED off.
;
/*NOTREACHED*/
}
void
sci4_init ()
{
// Start SCI4 module. SCI4はデフォルトでは無効化されているので有効にします。
*MSTPCRB &= ~(1 << 12);
//まず受信/送信を無効にします
// Disable transmit/receive.
*SCI (4, SCR) &= ~(SCR_TE | SCR_RE);
//周辺デバイスとしてポートを入力に使うので入力バッファの設定をします。
// Setup Input buffer. Use internal clock.
*P6_ICR &= ~1; //P60: SCI4 TxD
*P6_ICR |= 2; //P61: SCI4 RxD
//このモジュールの基本クロックを設定します。
// Clock select
*SCI (4, SCR) &= ~(SCR_CKE0 | SCR_CKE1); // Peripheral clock / 1
//シリアル通信のプロトコルを設定。ここでは調歩同期8bit Non Parity 1 Stop bit.
// Tx/Rx Format.
*SCI (4, SCMR) = 0; // Clocked synchronous mode.
*SCI (4, SMR) = 0; // 8N1
//ビットレートを決めるには周辺クロックがいくつかを決めないといけない。
//この基板の場合入力クロックは12MHzでMD_CLK=0。
//SCKCRデフォルトの場合CPUクロックは1/1で12MHz,周辺クロックも1/1で12MHz
// Bit rate.
// Input Clock: 12MHz
// CPU clock: 12MHz
// Peripheral clock 12MHz
// 12.* 1000000/(64/2 *38400) -1 = 8.77
*SCI (4, BRR) = 9; //38400bps
// Wait at least 1bit interval.
volatile int i;
for (i = 0; i < 0xffff; i++)
;
// Enable transmit/receive.
*SCI (4, SCR) |= (SCR_TE | SCR_RE);
}
int8_t
sci4_getc ()
{
uint8_t c;
while (((c = *SCI (4, SSR)) & (SSR_RDRF | SSR_ERR_BITS)) == 0)
;
if (c & SSR_ERR_BITS)
{
*SCI (4, SSR) &= ~(SSR_RDRF | SSR_ERR_BITS);
return 0;
}
c = *SCI (4, RDR);
*SCI (4, SSR) &= ~SSR_RDRF;
return c;
}
void
sci4_putc (int8_t c)
{
while ((*SCI (4, SSR) & SSR_TDRE) == 0)
;
*SCI (4, TDR) = c;
*SCI (4, SSR) &= ~SSR_TDRE;
// Wait transfer complete. これは今回の例ではなくてもい。
while ((*SCI (4, SSR) & SSR_TEND))
;
}
-*- mode: compilation; default-directory: "~/os/w/h8sx/board/test3/" -*-
Compilation started at Thu Apr 8 20:57:58
gmake romwrite
/usr/home/uch/os/w/tools/bin/h8300-elf-gcc -msx -fomit-frame-pointer -Wall -Werror -I../../../include -O2 -mint32 -Wp,-MD,.deps/start.P -c -o start.o start.c
/usr/home/uch/os/w/tools/bin/h8300-elf-ld -T ldscript -o test.elf entry.o start.o
/usr/home/uch/os/w/tools/bin/h8300-elf-objdump -x test.elf
test.elf: file format elf32-h8300
test.elf
architecture: h8300sx, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x00000100
Program Header:
LOAD off 0x00000074 vaddr 0x00000000 paddr 0x00000000 align 2**0
filesz 0x00000004 memsz 0x00000004 flags r--
LOAD off 0x00000078 vaddr 0x00000100 paddr 0x00000100 align 2**0
filesz 0x000002a0 memsz 0x000002a0 flags r-x
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 000002a0 00000100 00000100 00000078 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .start_vector 00000004 00000000 00000000 00000074 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
2 .comment 00000012 00000000 00000000 00000318 2**0
CONTENTS, READONLY
SYMBOL TABLE:
00000100 l d .text 00000000 .text
00000000 l d .start_vector 00000000 .start_vector
00000000 l d .comment 00000000 .comment
00000106 l .text 00000000 .L11
00000000 l df *ABS* 00000000 start.c
00000184 l .text 00000000 .L2
00000172 l .text 00000000 .L5
000001b6 l .text 00000000 .L9
000001d4 l .text 00000000 .L10
000001de l .text 00000000 .L36
000001fc l .text 00000000 .L12
00000206 l .text 00000000 .L35
00000224 l .text 00000000 .L14
0000022e l .text 00000000 .L34
0000024c l .text 00000000 .L16
00000256 l .text 00000000 .L33
00000274 l .text 00000000 .L18
0000027e l .text 00000000 .L32
0000029a l .text 00000000 .L20
000002a4 l .text 00000000 .L31
000002c0 l .text 00000000 .L22
000002f2 l .text 00000000 .L54
000002cc l .text 00000000 .L30
000002e8 l .text 00000000 .L25
00000314 l .text 00000000 .L26
0000032c l .text 00000000 .L27
0000033c l .text 00000000 .L56
00000360 l .text 00000000 .L57
00000378 l .text 00000000 .L62
00000394 l .text 00000000 .L63
00000196 g .text 000001a6 _machine_startup
00000378 g .text 00000028 _sci4_putc
0000033c g .text 0000003c _sci4_getc
00ffc000 g *ABS* 00000000 _stack_start
00000100 g .text 00000000 start
0000010c g .text 0000008a _sci4_init
/usr/home/uch/os/w/tools/bin/h8300-elf-objdump -D test.elf
test.elf: file format elf32-h8300
Disassembly of section .text:
00000100 <start>:
100: 7a 07 00 ff mov.l #0xffc000,er7
104: c0 00
00000106 <.L11>:
106: 5a 00 01 96 jmp @0x196:24
10a: 40 fa bra .-6 (0x106)
0000010c <_sci4_init>:
10c: 1a cf sub.l #0x4,er7
10e: 6b 22 00 ff mov.w @0xfffdca:32,r2
112: fd ca
114: e2 ef and.b #0xef,r2h
116: 6b a2 00 ff mov.w r2,@0xfffdca:32
11a: fd ca
11c: 6a 2a 00 ff mov.b @0xfffe92:32,r2l
120: fe 92
122: ea cf and.b #0xcf,r2l
124: 6a aa 00 ff mov.b r2l,@0xfffe92:32
128: fe 92
12a: 6a 2a 00 ff mov.b @0xfffb95:32,r2l
12e: fb 95
130: ea fe and.b #0xfe,r2l
132: 6a aa 00 ff mov.b r2l,@0xfffb95:32
136: fb 95
138: 6a 2a 00 ff mov.b @0xfffb95:32,r2l
13c: fb 95
13e: ca 02 or.b #0x2,r2l
140: 6a aa 00 ff mov.b r2l,@0xfffb95:32
144: fb 95
146: 6a 2a 00 ff mov.b @0xfffe92:32,r2l
14a: fe 92
14c: ea fc and.b #0xfc,r2l
14e: 6a aa 00 ff mov.b r2l,@0xfffe92:32
152: fe 92
154: 6a f0 00 ff mov.b #0x0,@0xfffe96:32
158: fe 96
15a: 6a f0 00 ff mov.b #0x0,@0xfffe90:32
15e: fe 90
160: 6a f9 00 ff mov.b #0x9,@0xfffe91:32
164: fe 91
166: 01 0d 07 00 mov.l #0x0,@er7
16a: 01 0e 07 20 cmp.l #0xfffe,@er7
16e: ff fe
170: 4e 12 bgt .+18 (0x184)
00000172 <.L5>:
172: 01 00 69 72 mov.l @er7,er2
176: 0a 9a add.l #0x1,er2
178: 01 00 69 f2 mov.l er2,@er7
17c: 01 0e 07 20 cmp.l #0xfffe,@er7
180: ff fe
182: 4f ee ble .-18 (0x172)
00000184 <.L2>:
184: 6a 2a 00 ff mov.b @0xfffe92:32,r2l
188: fe 92
18a: ca 30 or.b #0x30,r2l
18c: 6a aa 00 ff mov.b r2l,@0xfffe92:32
190: fe 92
192: 0a cf add.l #0x4,er7
194: 54 70 rts
00000196 <_machine_startup>:
196: 6a 2a 00 ff mov.b @0xffee50:32,r2l
19a: ee 50
19c: ca 08 or.b #0x8,r2l
19e: 6a aa 00 ff mov.b r2l,@0xffee50:32
1a2: ee 50
1a4: 6a 2a 00 ff mov.b @0xffee51:32,r2l
1a8: ee 51
1aa: ea f7 and.b #0xf7,r2l
1ac: 6a aa 00 ff mov.b r2l,@0xffee51:32
1b0: ee 51
1b2: 5e 00 01 0c jsr @0x10c:24
000001b6 <.L9>:
1b6: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
1ba: fe 94
1bc: 4c f8 bge .-8 (0x1b6)
1be: 01 7d 48 6f mov.b #0x6f,@0xfffe93:32
1c2: 00 ff fe 93
1c6: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
1ca: fe 94
1cc: ea 7f and.b #0x7f,r2l
1ce: 6a aa 00 ff mov.b r2l,@0xfffe94:32
1d2: fe 94
000001d4 <.L10>:
1d4: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
1d8: fe 94
1da: ea 04 and.b #0x4,r2l
1dc: 46 f6 bne .-10 (0x1d4)
000001de <.L36>:
1de: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
1e2: fe 94
1e4: 4c f8 bge .-8 (0x1de)
1e6: 01 7d 48 68 mov.b #0x68,@0xfffe93:32
1ea: 00 ff fe 93
1ee: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
1f2: fe 94
1f4: ea 7f and.b #0x7f,r2l
1f6: 6a aa 00 ff mov.b r2l,@0xfffe94:32
1fa: fe 94
000001fc <.L12>:
1fc: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
200: fe 94
202: ea 04 and.b #0x4,r2l
204: 46 f6 bne .-10 (0x1fc)
00000206 <.L35>:
206: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
20a: fe 94
20c: 4c f8 bge .-8 (0x206)
20e: 01 7d 48 61 mov.b #0x61,@0xfffe93:32
212: 00 ff fe 93
216: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
21a: fe 94
21c: ea 7f and.b #0x7f,r2l
21e: 6a aa 00 ff mov.b r2l,@0xfffe94:32
222: fe 94
00000224 <.L14>:
224: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
228: fe 94
22a: ea 04 and.b #0x4,r2l
22c: 46 f6 bne .-10 (0x224)
0000022e <.L34>:
22e: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
232: fe 94
234: 4c f8 bge .-8 (0x22e)
236: 01 7d 48 79 mov.b #0x79,@0xfffe93:32
23a: 00 ff fe 93
23e: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
242: fe 94
244: ea 7f and.b #0x7f,r2l
246: 6a aa 00 ff mov.b r2l,@0xfffe94:32
24a: fe 94
0000024c <.L16>:
24c: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
250: fe 94
252: ea 04 and.b #0x4,r2l
254: 46 f6 bne .-10 (0x24c)
00000256 <.L33>:
256: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
25a: fe 94
25c: 4c f8 bge .-8 (0x256)
25e: 01 7d 48 6f mov.b #0x6f,@0xfffe93:32
262: 00 ff fe 93
266: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
26a: fe 94
26c: ea 7f and.b #0x7f,r2l
26e: 6a aa 00 ff mov.b r2l,@0xfffe94:32
272: fe 94
00000274 <.L18>:
274: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
278: fe 94
27a: ea 04 and.b #0x4,r2l
27c: 46 f6 bne .-10 (0x274)
0000027e <.L32>:
27e: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
282: fe 94
284: 4c f8 bge .-8 (0x27e)
286: 6a fd 00 ff mov.b #0xd,@0xfffe93:32
28a: fe 93
28c: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
290: fe 94
292: ea 7f and.b #0x7f,r2l
294: 6a aa 00 ff mov.b r2l,@0xfffe94:32
298: fe 94
0000029a <.L20>:
29a: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
29e: fe 94
2a0: ea 04 and.b #0x4,r2l
2a2: 46 f6 bne .-10 (0x29a)
000002a4 <.L31>:
2a4: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
2a8: fe 94
2aa: 4c f8 bge .-8 (0x2a4)
2ac: 6a fa 00 ff mov.b #0xa,@0xfffe93:32
2b0: fe 93
2b2: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
2b6: fe 94
2b8: ea 7f and.b #0x7f,r2l
2ba: 6a aa 00 ff mov.b r2l,@0xfffe94:32
2be: fe 94
000002c0 <.L22>:
2c0: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
2c4: fe 94
2c6: ea 04 and.b #0x4,r2l
2c8: 46 f6 bne .-10 (0x2c0)
2ca: 40 26 bra .+38 (0x2f2)
000002cc <.L30>:
2cc: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
2d0: fe 94
2d2: 4c f8 bge .-8 (0x2cc)
2d4: 6a ab 00 ff mov.b r3l,@0xfffe93:32
2d8: fe 93
2da: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
2de: fe 94
2e0: ea 7f and.b #0x7f,r2l
2e2: 6a aa 00 ff mov.b r2l,@0xfffe94:32
2e6: fe 94
000002e8 <.L25>:
2e8: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
2ec: fe 94
2ee: ea 04 and.b #0x4,r2l
2f0: 46 f6 bne .-10 (0x2e8)
000002f2 <.L54>:
2f2: 6a 2b 00 ff mov.b @0xfffe94:32,r3l
2f6: fe 94
2f8: 17 63 extu.l #2,er3
2fa: 0f b2 mov.l er3,er2
2fc: ea 78 and.b #0x78,r2l
2fe: 47 f2 beq .-14 (0x2f2)
300: eb 38 and.b #0x38,r3l
302: 47 10 beq .+16 (0x314)
304: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
308: fe 94
30a: ea 87 and.b #0x87,r2l
30c: 6a aa 00 ff mov.b r2l,@0xfffe94:32
310: fe 94
312: 40 18 bra .+24 (0x32c)
00000314 <.L26>:
314: 6a 2b 00 ff mov.b @0xfffe95:32,r3l
318: fe 95
31a: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
31e: fe 94
320: ea bf and.b #0xbf,r2l
322: 6a aa 00 ff mov.b r2l,@0xfffe94:32
326: fe 94
328: 0c bb mov.b r3l,r3l
32a: 46 a0 bne .-96 (0x2cc)
0000032c <.L27>:
32c: 6a 2a 00 ff mov.b @0xffee51:32,r2l
330: ee 51
332: ca 08 or.b #0x8,r2l
334: 6a aa 00 ff mov.b r2l,@0xffee51:32
338: ee 51
33a: 54 70 rts
0000033c <_sci4_getc>:
33c: 6a 2b 00 ff mov.b @0xfffe94:32,r3l
340: fe 94
342: 17 63 extu.l #2,er3
344: 0f b2 mov.l er3,er2
346: ea 78 and.b #0x78,r2l
348: 47 f2 beq .-14 (0x33c)
34a: eb 38 and.b #0x38,r3l
34c: 47 12 beq .+18 (0x360)
34e: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
352: fe 94
354: ea 87 and.b #0x87,r2l
356: 6a aa 00 ff mov.b r2l,@0xfffe94:32
35a: fe 94
35c: f8 00 mov.b #0x0,r0l
35e: 54 70 rts
00000360 <.L57>:
360: 6a 2b 00 ff mov.b @0xfffe95:32,r3l
364: fe 95
366: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
36a: fe 94
36c: ea bf and.b #0xbf,r2l
36e: 6a aa 00 ff mov.b r2l,@0xfffe94:32
372: fe 94
374: 0c b8 mov.b r3l,r0l
376: 54 70 rts
00000378 <_sci4_putc>:
378: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
37c: fe 94
37e: 4c f8 bge .-8 (0x378)
380: 6a a8 00 ff mov.b r0l,@0xfffe93:32
384: fe 93
386: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
38a: fe 94
38c: ea 7f and.b #0x7f,r2l
38e: 6a aa 00 ff mov.b r2l,@0xfffe94:32
392: fe 94
00000394 <.L63>:
394: 6a 2a 00 ff mov.b @0xfffe94:32,r2l
398: fe 94
39a: ea 04 and.b #0x4,r2l
39c: 46 f6 bne .-10 (0x394)
39e: 54 70 rts
Disassembly of section .start_vector:
00000000 <.start_vector>:
0: 00 00 nop
2: 01 00 .word H'1,H'0
Disassembly of section .comment:
00000000 <.comment>:
0: 00 47 .word H'0,H'47
2: 43 43 .word H'43,H'43
4: 3a 20 mov.b r2l,@0x20:8
6: 28 47 mov.b @0x47:8,r0l
8: 4e 55 .word H'4e,H'55
a: 29 20 mov.b @0x20:8,r1l
c: 34 2e mov.b r4h,@0x2e:8
e: 33 2e mov.b r3h,@0x2e:8
10: 32 00 mov.b r2h,@0x0:8
/usr/home/uch/os/w/tools/bin/h8300-elf-objcopy -Osrec test.elf test.mot
../../h8sxwrite/h8sxwrite -f 12 -d 0 -m 0 test.mot
Output Device [ugen0]
H8SX Input Clock [12MHz]
MDCLK = 0
Send file [test.mot]: 1908 byte
vendor: 045b product: 0025
Flash memory size = 0x524288 byte
1905 byte. start addr=100
write 927/524288 byte
Success.
Compilation finished at Thu Apr 8 20:58:01
エコーバックを確認。
$ tip hmon38400
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ohayo
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